NXP Semiconductors /LPC408x_7x /TIMER0 /MR[0]

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Interpret as MR[0]

31282724232019161512118743000000000000000000000000000000000000000000MATCH

Description

Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.

Fields

MATCH

Timer counter match value.

Links

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